Integrated circuits (ICs) are enclosed within IC “packages.” The IC packages generally include a housing and external pads, connectors, leads or pins on outside edges or an outside surface of the housing. The external connectors are electrically connected to connection pads on IC dies for transferring electrical signals between the enclosed ICs and external components or devices with which the ICs interact. The IC packages are generally mounted on, Printed Circuit Boards (PCBs). A common practice is to directly surface attach the IC packages to the PCB with solder.
IC package designs differ based on a variety of characteristics, such as size, arrangement of external connectors and materials of construction, among many other characteristics. Each IC package must be appropriate for the enclosed IC, depending on IC characteristics such as die size, number of connection pads and amount of heat generated during operation of the chip, among other characteristics.
When a new IC or new IC package is developed, the package or IC/package combination must undergo testing to qualify the IC package to be used in a wide range of conditions. Additionally, particularly for surface-mounted IC packages, the IC package is tested when mounted on a representative circuit board that physically simulates the types of PCBs on which the IC package may be mounted. Such testing is necessary because the internal and external stresses and strains on a board-mounted IC package are different from a free-standing, or un-mounted, IC package. For example, it is important to determine the reliability of the “attach system” (i.e. solder balls, etc.) to the PCB. Also, the stresses on the IC die mounted within the IC package are different when the IC package is board-mounted compared to when the IC package is free-standing.
Tests that focus on the reliability or function of the connection between the IC package and the PCB are commonly referred to as “second-level” tests. On the other hand, tests that focus on internal portions of the IC package, when the IC packages are not attached to a PCB, are commonly referred to as “first-level” tests. However, the second-level tests commonly involve a combination of first-level and second-level issues, since the attached PCB can affect the IC die and other internal components of the IC package and the electrical signals applied to the external connectors must pass into the IC package to the IC die and back to the external connectors.
The second-level tests generally involve variations in electrical signal bias, ambient temperature, ambient humidity, etc. One commonly performed second-level IC package test is a thermal cycling test defined by IPC-9701, “Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments,” by IPC-Association Connecting Electronics Industries of Northbrook, Ill. In some instances, the Temperature, Humidity, Bias test (or a more extreme version known as Highly Accelerated Stress Testing (HAST)), which is normally performed as a first-level test, is performed as a second-level test.
The IPC-9701 test generally subjects the surface-mounted IC package to thermal cycling conditions while electrical signals are supplied to the IC package. The electrical signals are monitored for failure conditions, such as an unacceptable increase in electrical resistance at any given temperature (e.g. −60° C. to +125° C.), which may occur due to thermal expansion and/or contraction of any portion of the IC package. Manual testing then determines the location of the failure condition.
For the thermal-cycling portion of the testing, multiple IC packages 100 are surface mounted (e.g. soldered with a ball grid array) to a PCB 102, as shown in FIG. 1. Signal traces 104 are routed to the IC packages 100 from connectors 106 on the PCB 102. The PCB 102, populated with the IC packages 100, is placed in a thermal cycling chamber along with any other such populated PCBs, and the connectors 106 are connected to a data logger. The data logger supplies the electrical signals to the IC packages 100 through the connectors 106 and the signal traces 104. The data logger also monitors the response to the electrical signals (e.g. resistance, etc.) and the temperature in the chamber while the chamber cycles the temperature to which the PCB 102 and IC packages 100 are subjected.
To test the IC package, a relatively simple IC die is enclosed in the package and signals are transmitted through the package to a point on the IC die and back through the package from another point on the IC die. Thus, the external connectors, and associated internal components, are tested in pairs. However, the data logger typically has only a limited number of available channels for transmitting the electrical signals to the PCB 102. The IC packages 100, on the other hand, typically have many more external connectors than the data logger has channels. Therefore, for the thermal-cycling portion of the testing, the external connectors of the IC packages 100 are grouped together in multiple interconnected “chains” of external connectors. The length of each chain depends on the number of external connectors on each IC package 100, the number of IC packages 100 on the PCB 102 and the number of channels available in the data logger. Each channel of the data logger thus tests several chained-together external connectors and all of the internal pathways and connections associated therewith. The thermal-cycling portion of the testing, thus, gives a “gross” result for a general location of the failure condition. The manual portion of the testing, on the other hand, gives a “finer” result that associates the failure condition with one external connector or one pair of external connectors.
The PCB 102 includes cut lines 108 for cutting the mounted IC packages 100 from the PCB 102. In this manner, the IC packages 100 are removed from the PCB 102 without disconnecting the attach system (e.g. without slicing through the solder balls). The PCB 102 is thus left with a missing piece, as shown in FIG. 2. Therefore, after identifying an IC package 100 that is exhibiting potential failure conditions during the thermal-cycling portion of the testing, the PCB 102 is removed from the thermal cycling chamber and the identified IC package 100 is cut from the printed circuit board 102. The piece of the PCB 102 attached to the removed IC package 100 is then removed from or ground off the IC package 100 for the manual portion of the testing.
The identified IC package 100 is subjected to the manual testing to determine the cause or location of the failure condition. In this situation, a test operator manually probes each of the external connectors with a digital ohmmeter to test contact points and continuity of signals between two points, including resistance measurements.
The signal traces 104 are routed on the PCB 102 such that they will not be affected by the cutting of the PCB 102 upon the removal of any of the IC packages 100. Therefore, after removal of the identified IC package 100, the PCB 102, with the remaining IC packages 100 still mounted thereon, is generally returned to the thermal cycling chamber for further testing. The cutting of the PCB 102, however, takes away valuable time from the testing of the IC packages 100. Additionally, since the removed IC package 100 is permanently cut from the PCB 102, the removed IC package 100 cannot be returned to the thermal cycling portion of the testing to further subject the removed IC package 100 to additional thermal cycles and test for any other potential failures. The test operator, therefore, has to be sure that no additional thermal cycling is warranted on the identified IC package 100 before cutting it from the PCB 102. It is often difficult, however, to judge the right time to remove the identified IC package 100—too soon and some design weaknesses will go undetected, too late and test completion will be unnecessarily delayed.
The aforementioned HAST test generally subjects the IC packages to electrical bias testing in a relatively harsh environment (e.g. about 130° C. and about 85% relative humidity) to stress the IC packages to accelerate any potential electrochemical problems. The IC packages are placed in relatively expensive sockets that are mounted on a relatively expensive motherboard, and the populated motherboard is placed in a HAST test chamber. The IC packages are thus stressed in the test chamber for a period of time (e.g. about 100 hours). Then the populated motherboard is removed from the test chamber, and the IC packages are removed from the sockets. The IC packages are then connected to an Automated Test Equipment (ATE) and tested to locate any failure condition(s) that may have been caused by the electrical bias stressing. An improvement to this test apparatus and method is described in U.S. Pat. No. 6,597,189, filed Nov. 27, 2002 and issued Jul. 22, 2003 to the same inventor and assigned to the same assignee as the present invention. The disclosure of this US patent is incorporated herein by this reference. In the background thereof, the U.S. Pat. No. 6,597,189 describes a HAST test using sockets as briefly mentioned above. The U.S. Pat. No. 6,597,189 also describes a socketless test apparatus and method using test interposer cards on which the IC packages are mounted and which is an improvement over the socket-based tests.
The test interposer cards described in the U.S. Pat. No. 6,597,189 are appropriate PCB for testing the IC packages in a board-mounted situation. The test interposer cards have edge connectors on two opposing edges for connecting to mating female clamps on the motherboard with which the t st interposer cards and the IC packages are connected parallel to the motherboard.
It is with respect to these and other considerations that the present invention has evolved.